1. Field of the Invention
The present invention relates to a flash memory device, voltage generating circuit of the flash memory device, and a method for facilitating programming of the flash memory device.
2. Description of the Related Art
A flash memory device is a particular type of non-volatile electrically erasable programmable read-only memory (EEPROM) device which does not require a refresh function. The flash memory device may be classified into a NOR type and a NAND type. The NOR type is primarily used to store a small amount of information at high speeds, while the NAND type is mainly used to store a larger amount of information.
FIG. 1 is a block diagram illustrating a prior art NAND-type flash memory device. Referring to FIG. 1, a typical NAND-type flash memory device 100 includes a memory cell array 12, a row decoder 14 and a page buffer circuit 16. The memory cell array 12 includes a plurality of cell strings. A given cell string 121 includes a string selection transistor (SST) connected to a bit-line BL1, a ground selection transistor (GST) connected to a common source line (CSL), and a plurality of memory cells M1-Mm. The plurality of memory cells M1-Mm are serially connected between the SST and the GST. A gate of the SST is connected to a string selection line (SSL), and a gate of the GST is connected to a ground selection line (GSL).
The plurality of memory cells M1-Mm are transistors, each of which has a floating gate and a control gate. The control gates of memory cells M1-Mm in each row are connected to a corresponding word line of a plurality of word lines WL1-WLm output from the row decoder 14. A row of memory cells connected to a single word line is referred to as a page. For example, a row of memory cells M1 connected to the word line WL1 corresponds to a page 122.
A plurality of bit lines BL1-BLn is connected to the page buffer circuit 16. The page buffer circuit 16 is a register circuit used to read/store a large amount of data within a short period of time. Data input from the outside is stored in the memory cell array 12 through the page buffer circuit 16, and data output from the memory cell array 12 is output to the outside through the page buffer circuit 16.
Respective memory cells M1-Mm are programmed by applying a high program voltage to the control gates of the memory cells M1-Mm, setting a predetermined voltage on the BL1, and controlling threshold voltages of cell transistors. To program the memory cells M1-Mm, a corresponding SST must be turned on. Thus, a voltage on the bit line BL1 must be less than a voltage (Vssl−Vth_sst) obtained by subtracting a threshold voltage (Vth_sst) of the SST from a voltage (Vssl) on the SSL.
On the other hand, the SST must be turned off to prevent the memory cells M1-Mm from being programmed. Therefore, the voltage on the bit line BL1 must be greater than the voltage (Vssl−Vth_sst) obtained by subtracting a threshold voltage (Vth_sst) of the SST from a voltage (Vssl) on the SSL. In programming of the memory cells M1-Mm, the voltage Vssl on the SSL is typically set to a supply voltage Vcc, and the voltage on the BL1 is typically set to a ground voltage or a specific voltage higher than the ground voltage.
FIG. 2 illustrates a graph showing the relationship among the voltage Vblc on the BL1, the voltage Vssl on the SSL, and the supply voltage Vcc in programming of the prior art NAND-type flash memory device 100. Referring to FIG. 2, the voltage Vssl on the SSL is proportional to Vcc. The voltage on BL1 has a specific voltage level of Vblc.
However, the level of Vcc may be changed due to noise or other factors. If the level of Vcc is changed, the level of the voltage Vssl on the SSL is also changed. If the Vssl on the SSL decreases due to the decrease in Vcc, while the voltage on the BL1 is fixed to the specific level of Vblc, the SST does not turned on. In this case, the memory cells in the prior art NAND-type flash memory device 100 cannot be programmed.
In FIG. 2, C1 represents a case where the difference between the voltage Vssl on the SSL and the voltage Vblc on the BL1 is greater than the threshold voltage Vth_sst. In such a case it is possible to program the memory cells. C2 represents a case where the difference between the voltage Vssl on the SSL and the voltage Vblc is less than the threshold voltage Vth_sst of the SST. In this case, it is not possible to program the memory cells. In other words, if Vcc is less than a given voltage Vp (as shown by the dotted line in FIG. 2), it is not possible to program the memory cells. Accordingly, a programming error may occur when memory cells that are to be programmed cannot be programmed.